RISC-V at Embedded World

The open standard RISC-V Instruction Set Architecture (ISA) offers developers new design freedoms for an optimized processor with all the benefits and advantages of full ecosystem support. RISC-V verification requires both functional tests and compliance to the ISA specification. Now all adopters that choose to explore the new design freedoms of
RISC-V will also need to consider the challenge of RISC-V verification.

This talk highlights the open standards such as RVVI (RISC-V Verification Interface) for test bench infrastructure that is supported with additional freely available resources with test suites, coverage libraries, and other Verification IP.
This talk also will review the latest approaches for RISC-V verification including vector extension, PMP, crypto, privilege, and custom instructions with the ‘lock-step-compare’ method that supports asynchronous events and debug operations.