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Tuesday, March 14 • 10:30 - 10:45
Introduction to RISC-V Processor Verification - Larry Lapides, Imperas Software Ltd

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The open standard RISC-V Instruction Set Architecture (ISA) offers developers new design freedoms for an optimized processor with all the benefits and advantages of full ecosystem support. RISC-V verification requires both functional tests and compliance to the ISA specification. Now all adopters that choose to explore the new design freedoms of
RISC-V will also need to consider the challenge of RISC-V verification.

This talk highlights the open standards such as RVVI (RISC-V Verification Interface) for test bench infrastructure that is supported with additional freely available resources with test suites, coverage libraries, and other Verification IP.
This talk also will review the latest approaches for RISC-V verification including vector extension, PMP, crypto, privilege, and custom instructions with the ‘lock-step-compare’ method that supports asynchronous events and debug operations.

avatar for Larry Lapides

Larry Lapides

Vice President Sales, Imperas Software
Prior to joining Imperas, Larry ran sales at Averant and Calypto Design Systems. He was vice president of worldwide sales during the run-up to Verisity's IPO (the top performing IPO of 2001), and afterwards as Verisity solidified its position as the fifth largest EDA company. Before... Read More →

Tuesday March 14, 2023 10:30 - 10:45 CET
Hall 4A, Stand 4A-620